This invention relates in general to multi-requester arbitration circuits for arbitrating between multiple request signals, and in particular, for arbitrating between multiple asynchronous request signals.
In present digital electronics systems, especially those which are computer based, there is often a need to provide arbitration between more than one requester which needs service from a general system resource. For example, a typical prior art system can have two or more computer processors which must share a common system bus or a common system memory. Computer processors are hereinafter referred to as "requesters of service," and the bus, memory, or other device is hereinafter referred to as "a general system resource." It is common that requests from the computer processors do not occur simultaneously in time, but rather occur asynchronously.
One prior art arbitration technique is to synchronize the asynchronous requests to a free running clock. A request is clocked into a first rank flip-flop, which is then clocked into a second rank flip-flop. Several drawbacks exist for this method. Since the output of the first flip-flop can go metastable, the clock period must be much greater than the propagation delay through the first flip-flop. If this is not provided, then the metastability at the output of the first flip-flop could be transferred into the second flip-flop. However, the settling of any metastability cannot be guaranteed to be stable within any given time period. Rather, the first flip-flop would be stable within some time period for some statistical probability of clocked events. Thus, synchronization is relatively slow and is not guaranteed correct every time.
Another prior art synchronization technique is to clock a request into three ranks of flip-flops, and provide a voting technique to determine if arbitration decisions are accurate. However, there is still a statistical probability of an arbitration error occurring.